module detektor(iCLK,iRESTART,iBit,oY);
input iCLK,iRESTART,iBit;
output reg oY;

reg [1:0] rCSTATE,rNSTANE;

parameter= S0=2'b00, S1=2'b01, S2=2'b10;

always@(posedge iCLK or posedge iRESTART)
if(iRESTART)
rCSTATE<=S0;
else
rCSTATE<=rNSTANE;

always@(rCSTATE or iBit)
if(rCSTATE==S0 && iBit==0)
rNSTANE=S0;
else if(rCSTATE==S0 && iBit==1)
rNSTANE=S1;
else if(rCSTATE==S1 && iBit==0)
rNSTANE=S0;
else if(rCSTATE==S1 && iBit==1)
rNSTANE=S2;
else if(rCSTATE==S2 && iBit==0)
rNSTANE=S0;
else if(rCSTATE==S2 && iBit==1)
rNSTANE=S2;

always@(rCSTATE or iBit)
if(rCSTATE==S2 && iBit==0)
oY=1;
else
oY=0;

endmodule